In some conventional systems, design for testability is a core principle. This may include design techniques which enable testing to be done quickly and cost effectively, and to identify the source of any faults that may impair the normal operation of the system. One of the first standards for integrated circuit (IC) components was initiated in 1985 by an ad hoc group composed of representatives from key electronics manufacturers which called itself the Joint Action Test Group (JTAG). The agreements developed by this group were eventually adopted as a standard by the Institute of Electrical and Electronics Engineers (IEEE) in resolution IEEE 1149.1-1990, “IEEE Standard Test Access Port and Boundary-Scan Architecture”, a standard which is more commonly known by the eponymous name “JTAG”.
IC devices which implement JTAG may have two fundamental modes of operation: normal mode, in which signals pass from normal inputs to normal outputs, and boundary scan mode, generally used for testing, in which signals may be input to an IC via the JTAG input debug interface and output from the device via the JTAG output debug interface. JTAG defines a physical debug interface known as a test access port (TAP) which comprises 4, and optionally 5 serial interfaces. Test data input (TDI) is the serial interface through which debug messages are sent to an IC device. Test data output (TDO) is the serial interface through which debug messages are output from an IC device. Test mode select (TMS) which is a signal that sets the operating mode for the device when executing in boundary scan mode. Finally, test clock (TCLK) which provides the operating clock for devices in boundary scan mode. An optional input on the TAP interface is the test reset (TRST) which interrupts an ongoing boundary scan test sequence.
Debug messages may consist of instructions and data which are sent via the TDI or received via the TDO. Debug messages may be processed within an IC by a JTAG TAP controller which is responsible for the execution of JTAG instructions on the IC device. The destination for debug messages may be a series of registers within the IC. These may include an instruction register, where a JTAG instruction may select one of a plurality of data registers which are to receive data from the TDI and to output data to the TDO. A third type of register is referred to as a bypass register. When this register is selected, the IC may ignore debug messages. Instructions which are not recognized as legitimate JTAG instructions by the JTAG TAP controller may result in subsequent debug messages being ignored by the IC.
As circuit boards and devices become more complex and made use of inexorably more complicated embedded processors, efforts arose to adapt JTAG for use with embedded hardware and software systems. While these adaptations used many of the same concepts, and even signal names, from JTAG, they had different objectives. JTAG may be largely concerned with validating electrical continuity in boards and in IC devices, while JTAG adaptations for embedded systems may seek to extend capabilities found in in-circuit emulation (ICE) systems to devices in which a processor core resides on a system on a chip (SOC) device where the pins from the SOC may not provide direct connectivity to the processor core. One notable JTAG adaptation is known as enhanced (or alternately, extended) JTAG, or EJTAG. EJTAG provides capabilities to set hardware and software breakpoints, to single step through executable code, and to access the contents of internal registers and on-chip memory areas. EJTAG may allow the debug software to be resident in application software, or in an external EJTAG probe. In the latter case, references to the virtual memory area assigned to EJTAG memory are converted into transactions on the TAP interface. EJTAG may use a TAP interface in which signals have the same names and definitions as in the JTAG TAP The EJTAG TAP controller may be responsible for the execution of EJTAG instructions on the processor core. The JTAG instruction set may contain no instruction codes which are recognizable as legitimate EJTAG instruction codes. Similarly the EJTAG instruction set may contain no instruction codes which are recognizable as legitimate JTAG instruction codes. Thus, a JTAG TAP controller may ignore received debug messages which contain EJTAG instructions, while a EJTAG TAP controller may ignore received debug messages which contain JTAG instructions.
In an example of operation, the EJTAG probe may poll an EJTAG control register through the TAP. The EJTAG control register may contain information that indicates when a processor action is pending. The physical address of the transaction may be available in the EJTAG address register. The EJTAG data register is then accessed by the EJTAG probe to get data if the desired action is a write, and to provided data if the desired action is a read. The EJTAG control register may be subsequently updated to indicate that the processor action has been completed.
As embedded systems become ever more complex, systems on chips (SOCs) are evolving to include multiple processor cores in the same device. In some application specific standard products (ASSP) targeted for secure wireless communications applications, a device may contain a general purpose processor core and an ancillary processor core which is adapted for digital signal processing (DSP). These multiple processor core architectures present a number of challenges for on-chip debugging. A conventional method of on-chip debugging of a SOC with two processor cores, where GP1 refers to a general purpose processor core, and SP2 refers to an application specific processor core, may involve a configuration in which GP1 and SP2 are daisy chained. This may entail coupling the TDI from an EJTAG probe to the TDI at GP1, the TDO from GP1 being coupled to the TDI at SP2, and the TDO from SP2 being coupled to the TDO at the EJTAG probe. Such chaining of EJTAG and/or JTAG components is also known as a scan chain.
As scan chains become longer with ever increasing numbers of processor cores being included in a single SOC device, the speed of EJTAG access to some processor cores may become a limitation to effective on-chip debugging. An alternative to a long scan chain may be to divide the chain into a plurality of shorter scan chains but this may result in increased device pin count to enable access to multiple scan chains. In addition, a plurality of JTAG interfaces in a single device may require additional external debugging hardware, and circuitry adapted to controlling the selection of JTAG interfaces to test at any given instant in time.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.